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Modeling and Simulation of 12.5 Gb/s on a HyperBGA® Package


Publisher: Endicott Interconnect
Overview:
Demonstrating that current HyperBGA® technology meets the performance requirements for applications running at speeds of 12.5 Gbps per channel, this paper presents high-speed/high-frequency modeling and simulation results for company's HyperBGA® organic chip-carrier package. An overview of the HyperBGA PTFE-based chip carrier technology is provided along with an illustration of a typical HyperBGA module cross section. Modeling and simulation methodology is described in detail, and frequency domain analysis is explained with the help of diagrams and graphical representations. Results of time domain analysis are reviewed and eye diagram simulation results are depicted as graphs.
TABLE OF CONTENTS
1.Technology Overview1
2.Introduction to Modeling and Simulation Methodology1
3.Frequency Domain Analysis2
4.Time Domain Analysis3
5.Conclusions4
6.References5
7.Figures
7.1.Figure 1: Typical HyperBGA® Module Cross-Section1
7.2.Figure 2: Timing Diagram Showing a Sinusoidal Approximation of Non Return to Zero Level Signaling (NRZ-L) at 12.5 Gb/s2
7.3.Figure 3: Drawing of HyperBGA® Full Signal Path from C4 to BGA (Not Drawn to Scale)3
7.4.Figure 4: Full Package Path Model of a Selected Differential Pair3
7.5.Figure 5: Differential-Mode S-Parameter Data3
7.6.Figure 6: Ansoft Serenade® Schematic for Generating a Differential Eye Diagram That Utilizes S-Parameter Data4
7.7.Figure 7: Eye Diagram Simulation Results4
7.8.Figure 8: Zoomed-in Eye Diagram Results at a 0V Cross-over4
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